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Data Sheet 26301.102b
3935
Package ED, 44-Pin PLCC
3-PHASE POWER MOSFET CONTROLLER -- For Automotive Applications
The A3935 is designed specifically for automotive applications that require high-power motors. Each provides six high-current gate drive outputs capable of driving a wide range of n-channel power MOSFETs. A requirement of automotive systems is steady operation over a varying battery input range. The A3935 integrates a pulse-frequency modulated boost converter to create a constant supply voltage for driving the external MOSFETs. Bootstrap capacitors are utilized to provide the above battery supply voltage required for n-channel FETs. Direct control of each gate output is possible via six TTL-compatible inputs. A differential amplifier is integrated to allow accurate measurement of the current in the three-phase bridge.
Package JP, 48-Pin LQFP
Package LQ, 36-Pin SOIC
Diagnostic outputs can be continuously monitored to protect the driver from short-to-battery, short-to-supply, bridge-open, and battery under/overvoltage conditions. Additional protection features include dead-time, VDD undervoltage, and thermal shutdown. The A3935 is supplied in a choice of three packages, a 44-lead PLCC with copper batwing tabs (suffix ED), a 48-lead low profile QFP with exposed thermal pad (suffix JP), and a 36-lead 0.8 mm pitch SOIC (suffix LQ).
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltages, VBAT, VDRAIN, VBOOST, BOOSTD ... -0.6 V to 40 V Output Voltage Ranges, GHA/GHB/GHC, VGHX .. -4 V to 55 V SA/SB/SC, VSX ............... -4 V to 40 V GLA/GLB/GLC, VGLX .... -4 V to 16 V CA/CB/CC, VCX .......... -0.6 V to 55 V Sense Circuit Voltages, CSP,CSN, LSS ............... -4 V to 6.5 V Logic Supply Voltage, VDD ........................... -0.3 V to +6.5 V Logic Input/Outputs and OVSET, BOOSTS, CSOUT, VDSTH ......... -0.3 V to 6.5 V Operating Temperature Range, TA ........................... -40C to +135C Junction Temperature, TJ ........... +150C Storage Temperature Range, TS ........................... -55C to +150C
* Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided.
FEATURES ! Drives wide range of n-channel MOSFETs in 3-phase bridges ! PFM boost converter for use with low-voltage battery supplies ! Internal LDO regulator for gate-driver supply ! Bootstrap circuits for high-side gate drivers ! Current monitor output ! Adjustable battery overvoltage detection. ! Diagnostic outputs
Motor lead short-to-battery, short-to-ground, and bridge-open protection ! Undervoltage protection ! -40 C to +150 C, TJ operation ! Thermal shutdown
!
Always order by complete part number, e.g., A3935KLQ .
3935 THREE-PHASE POWER MOSFET CONTROLLER
Functional Block Diagram
See pages 8 and 9 for terminal assignments and descriptions.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 2003 Allegro MicroSystems, Inc.
3935 THREE-PHASE POWER MOSFET CONTROLLER
A3935KED (PLCC)
A3935KLQ (SOIC)
* Measured on "High-K" multi-layer PWB per JEDEC Standard JESD51-7. Measured on typical two-sided PWB with power tabs (terminals 1, 2, 11, 12, 22, 23, 34, and 35) connected to copper foil with an area of 3.8 square inches (2452 mm2) on each side. See Application Note 29501.5, Improving Batwing Power Dissipation, for additional information.
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3935 THREE-PHASE POWER MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40C to +150C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits Characteristics Power Supply VDD Supply Current VBAT Supply Current Battery Voltage Operating Range Bootstrap Diode Forward Voltage IDD IBAT VBAT VDBOOT IDBOOT = -Icx = 10 mA, VDBOOT = VREG - VCX IDBOOT = -Icx = 100 mA Bootstrap Diode Resistance Bootstrap Diode Current Limit Bootstrap Quiescent Current Bootstrap Refresh Time VREG Output Voltage 1 VREG Dropout Voltage 2 Gate Drive Avg. Supply Current VREG Input Bias Current Boost Supply VBOOST Output Voltage Limit VBOOST Output Volt. Limit Hyst. Boost Switch ON Resistance Max. Boost Switch Current Boost Current Limit Threshold Volt. OFF Time Blanking Time VBOOSTM VBOOSTM rDS(on) IBOOSTSW VBI(th) toff tblank Increasing VBOOSTS IBOOSTD < 300 mA VBAT = 7 V 14.9 35 - - 0.45 3.0 100 - - 1.4 - - - - 16.3 180 3.3 300 0.55 8.0 220 V mV mA V s ns rDBOOT IDM ICX trefresh VREG VREGDO IREG IREGBIAS rD(100 mA) = [VD(150 mA) - VD(50 mA)]/100 mA 3 V < [VREG - VCX] < 12 V VCX = 40 V, GHx = ON VSX = low to guarantee V = +0.5 V refresh of 0.47 F Boot Cap at Vcx - Vsx = +10 V VBAT = 7 V to 40 V, VBOOST from Boost Reg VREGDO = Vboost - Vreg, Ireg = 40 mA No external dc load at VREG, CREG = 10 F Current into VBOOST, ENABLE = 0 All logic inputs = 0 V All logic inputs = 0 V - - 7.0 0.8 1.5 2.5 -150 10 - 12.7 - - - - - - - - - - - - - 0.9 - - 7.0 3.0 40 2.0 2.3 7.5 -1150 30 2.0 14 - 40 4.0 mA mA V V V mA A s V V mA mA Symbol Conditions Min Typ Max Units
NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. 1. For VBOOSTM < VBOOST < 40 V power dissipation in the VREG LDO increases. Observe TJ < 150 C limit. 2. With VBOOST decreasing Dropout Voltage measured at VREG = VREGref - 200 mV where VREG(ref) = VREG at VBOOST = 16 V.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
Continued next page ...
3935 THREE-PHASE POWER MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40C to +150C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Characteristics Control Logic Logic Input Voltages Logic Input Currents Input Hysteresis Logic Output High Voltage Logic Output Low Voltage Output High Voltage Source Current (pulsed) Source ON Resistance VI(1) VI(0) II(1) II(0) Vhys VO(H) VI(L) VDSL(H) IxU rSDU(on) IO(H) = -800 A IO(L) = 1.6 mA GHx: IxU = -10 mA, Vsx = 0 GLx: IxU = -10 mA, Vlss = 0 VSDU = 10 V, TJ = 25 C VSDU = 10 V, TJ = 135 C IxU = -150 mA, TJ = 25 C IxU = -150 mA, TJ = 35 C Gate Drives, GLx ( internal SINK or lower switch stages) Sink Current (pulsed) Sink ON Resistance Gate Drives, GHx, GLx (General) Phase Leakage (Source) Propagation Delay, Logic only Output Skew Time Dead Time (Shoot-Through Prevention) ISx tpd tsk(o) tdead ENABLE = 0, VSx = 1.7 V Logic input to unloaded GHx, GLx Grouped by edge, phase-to-phase Between GHx, GLx transitions of same phase 0 - - 75 - - - - 100 150 50 180 A ns ns ns IxL rDSL(on) VDSL = 10 V, TJ = 25 C VDSL = 10 V, TJ = 135 C IxL = +150 mA, TJ = 25 C IxL = +150 mA, TJ = 135 C - 550 1.8 3.0 850 - - - - - 6.0 7.5 mA mA Minimum high level input for logical "one" Maximum low level input for logical "zero" VI = VDD VI = 0.8 V 2.0 - - 50 100 VDD - 0.8 - VREG - 2.26 VREG - 0.26 - 400 4.0 7.0 - - - - - - - - - 800 - - - - 0.8 500 - 300 - 0.4 VREG VREG - - 10 15 V V A A mV V V V V mA mA Symbol Conditions Limits Min Typ Max Units
Gate Drives, GHx ( internal SOURCE or upper switch stages)
NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. For GHX: VSDU = VCX - VGHX, VDSL = VGHX - VSX, VDSL(H) = VCX - VSDU - VSX. For GLX: VSDU = VREG - VGLX, VDSL = VGLX - VLSS, VDSL(H) = VREG - VSDU - VLSS.
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3935 THREE-PHASE POWER MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40C to +150C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits Characteristics Sense Amplifier Input Bias Current Input Offset Current Input Resistance Ibias IIO ri CSP = CSN = 0 V CSP = CSN = 0 V CSP with respect to GND CSN with respect to GND Diff. Input Operating Voltage Output Offset Voltage Output Offset Voltage Drift Input Com-Mode Oper. Range Voltage Gain Low Output Voltage Error DC Common-Mode Attenuation Output Resistance Output Dynamic Range Output Current, Sink Output Current, Source VDD Supply Ripple Rejection VREG Supply Ripple Rejection Small Signal 3-dB Bandwidth AC Common-Mode Attenuation Output Slew Rate (positive or negative) VID VOO VOO VIC AV Ev AVC ro VCSOUT Isink Isource PSRR PSRR f3db Avc SR VID = CSP - CSN, -1.3V < CSP,N < 4V CSP = CSN = 0 V CSP = CSN = 0 V CSP = CSN VID = 40 mV to 200 mV Vid = 0 to 40 mV, Vo = (19.2 x VID) + Vo + Ev CSP = CSN = 200 mV VCSOUT = 2.0 V ICSOUT = -100 A at top rail, 100 A at bottom rail VCSOUT = 2.5 V VCSOUT = 2.5 V CSP = CSN = GND, freq. = 0 to 1 MHz CSP = CSN = GND, freq. = 0 to 300 kHz 10 mV input Vcm = 250 mV/pp, freq. = 0 to 800 kHz 200 mV step input, meas. 10/90% points -180 - - - - 77 - -1.5 18.6 - 28 - 0.075 20 -1.0 20 45 - 26 10 - - 80 4.0 - 250 100 - 19.2 - - 8.0 - - - - - 1.6 - - -360 35 - - 200 450 - 4.0 19.8 25 - - VDD-0.25 - - - - - - - A A k k mV mV V/C V V/V mV dB V mA mA dB dB MHz dB V/s Symbol Conditions Min Typ Max Units
NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3935 THREE-PHASE POWER MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40C to +150C, VBAT = 7 V to 16 V,
VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active.
Limits Characteristics Fault Logic VDD Undervoltage VDD Undervoltage Hysteresis OVSET Operating Volt. Range OVSET Calibrated Volt. Range OVSET Input Current Range VBAT Overvoltage Range VBAT Overvoltage VBAT Overvoltage Hysteresis VBAT Overvoltage Gain Constant VBAT Undervoltage VBAT Undervoltage Hysteresis VREG Undervoltage VDSTH Input Range VDSTH Input Current Short-to-Ground Threshold Short-to-Battery Threshold VDRAIN /Open Bridge Oper. Range VDRAIN /Open Bridge Current VDRAIN /Open Bridge Threshold Volt. Thermal Shutdown Temp. Thermal Shutdown Hysteresis VDD(uv) VDD(uv) VSET(ov) VSET(ov) ISET(ov) VBAT(ov) VBAT(ov) VBAT(ov) KBAT(ov) VBAT(uv) VBAT(uv) VREG(uv) VDSTH IDSTH VSTG(th) VSTB(th) VDRAIN IVDRAIN VBDGO(th) TJ TJ VDSTH > 0.8 V With a high-side driver "on", as VSX decreases, VDRAIN - VSX > VSTG causes a fault With a low-side driver "on", as VSX increases, VSX - VLSS > VSTB causes a fault 7 V < VBAT < 40 V 7 V < VBAT < 40 V If VDRAIN < VBDGOTH then a bridge fault occurs 0 V < VSET(ov) < 2.5 V Increasing VBAT, VSET(ov) = 0 V Percent of VBAT(ov) value set by VSET(ov) VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov) [0] Decreasing VBAT Percent of VBAT(uv) Decreasing VREG Decreasing VDD VDD(recovery) - VDD(uv) 3.8 100 0 0 -1.0 19.4 19.4 9.0 - 5.0 8.0 9.9 0.5 40 VDSTH-0.3 VDSTH-0.3 -0.3 0 1.0 160 7.0 - - - - - - 22.4 - 12 5.25 - - - - 4.3 300 VDD 2.5 +1.0 40 25.4 15 - 5.5 12 11.1 3.0 100 V mV V V A V V % V/V V % V V A V V V mA V C C Symbol Conditions Min Typ Max Units
- VDSTH+0.2 - VDSTH+0.2 - - - 170 10 VBAT+2.0 1.0 3.0 180 13
NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal.
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3935 THREE-PHASE POWER MOSFET CONTROLLER
Terminal Functions
Terminal Name CSP VDSTH LSS GLC SC GHC CC GLB SB GHB CB GLA SA GHA CA VREG VDRAIN VBOOST BOOSTS BOOSTD VBAT UVFLT OVFLT FAULT ALO AHI BHI BLO CLO CHI ENABLE OVSET NC CSOUT VDD CSN GND Function Current-sense input, positive-side DC input, drain-to-source monitor threshold voltage Gate-drive source return, low-side Gate-drive C output, low-side Load phase C input Gate-drive C output, high-side Bootstrap capacitor C Gate-drive B output, low-side Load phase B input Gate-drive B output, high-side Bootstrap capacitor B Gate-drive A output, low-side Load phase A input Gate-drive A output, high-side Bootstrap capacitor A Gate drive supply, positive Kelvin connection to MOSFET high-side drains Boost supply output Boost switch, source Boost switch, drain Battery supply, positive VBAT undervoltage fault output VBAT overvoltage fault output Active-low fault output, primary Gate control input A, low-side Gate control input A, high-side Gate control input B, high-side Gate control input B, low-side Gate control input C, low-side Gate control input C, high-side Gate output enable DC input, overvoltage threshold setting for VBAT Not connected, no external connection allowed Current-sense amplifier output Logic supply, nominally +5 V Current-sense input, negative-side Ground, dc supply returns, negative, and (for ED package) heat sink tab A3935KED (PLCC) 31 32 33 36 37 38 39 40 41 42 43 44 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 24 25 26 27 28 29 30 1, 2, 11, 12, 22, 23, 34, 35 A3935KJP (QLFP) 19 20 21 22 26 27 28 29 30 31 32 33 34 38 39 40 41 42 43 44 46 3 4 5 6 7 8 9 10 11 12 15 1,2,13,14,23,24, 25,35,36,37,47,48 16 17 18 45 34 35 36 21 A3935KLQ (SOIC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 33 -
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3935 THREE-PHASE POWER MOSFET CONTROLLER
Terminal Descriptions
AHI/BHI/CHI. Direct control of high-side gate outputs GHA/ GHB/GHC. Logic "1" drives the gate "on". Logic "0" pulls the gate down, turning off the external power MOSFET. Internally pulled down when terminal is open. ALO/BLO/CLO. Direct control of low-side gate outputs GLA/ GLB/GLC. Logic "1" drives the gate "on". Logic "0" pulls the gate down, turning off the external power MOSFET. Internally pulled down when terminal is open. BOOSTD. Boost converter switch drain connection. BOOSTS. Boost converter switch source connection. CA/CB/CC. High-side connection for bootstrap capacitor, positive supply for high-side gate drive. The bootstrap capacitor is charged to VREG when the output Sx terminal is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for nchannel power MOSFETs. CSN. Input for current-sense, differential amplifier, inverting, negative side. Kelvin connection for ground side of currentsense resistor. CSOUT. Amplifier output voltage proportional to current sensed across an external low-value resistor placed in the ground-side of the power FET bridge. CSP. Input for current-sense differential amplifier, noninverting, positive side. Connected to positive side of sense resistor. ENABLE. Logic "0" disables the gate control signals and switches off all the gate drivers "low" causing a "coast". Can be used in conjunction with the gate inputs to PWM the load current. Internally pulled down when terminal is open. FAULT. Diagnostic logic output signal, when "low" indicates that one or more fault condition have occurred. GHA/GHB/GHC. High-side gate-drive outputs for n-channel MOSFET drivers. External series gate resistors can control slew rate seen at the power driver gate; thereby, controlling the di/dt and dv/dt of Sx outputs. GLA/GLB/GLC. Low-side gate drive outputs for external, nchannel MOSFET drivers. External series gate resistors can control slew rate. GND. Ground or negative side of VDD and VBAT supplies. LSS. Low-side gate driver returns. Connects to the common sources in the low-side of the power MOSFET bridge. OVFLT. Logic "1" means that the VBAT exceeded the VBAT overvoltage trip point set by OVSET level. It will recover after a hysteresis below that maximum value. Normally has a highimpedance state. OVSET. A positive, dc level that controls the VBAT overvoltage trip point. Usually, provided from precision resistor divider network between VDD and GND, but can be held grounded for a preset value. When terminal is open, sets unspecified but high overvoltage trip point. SA/SB/SC. Directly connected to the motor terminals, these terminals sense the voltages switched across the load and are connected to the negative side of the bootstrap capacitors. Also, are the negative supply connection for the floating, high-side drivers. UVFLT. Logic "1" means that VBAT is below its minimum value and will recover after a hysteresis above that minimum value. Has a high-impedance state. [If UVFLT and OVFLT are both in high-impedance state; then, at least, a thermal shutdown or VDD undervoltage has occurred.] VBAT. Battery voltage, positive input and is usually connected to the motor voltage supply. VBOOST. Boost converter output, nominally 16 V, is also input to regulator for VREG. Has internal boost current and boost voltage control loops. In high-voltage systems is approximately one diode drop below VBAT. VDD. Logic supply, nominally +5 V. VDRAIN. Kelvin connection for drain-to-source voltage monitor and is connected to high-side drains of MOSFET bridge. High impedance when terminal is open and registers as a short-to-ground fault on all motor phases. VDSTH. A positive, dc level that sets the drain-to-source monitor threshold voltage. Internally pulled down when terminal is open. VREG. High-side, gate-driver supply, nominally, 13.5 V. Has low-voltage dropout (LDO) feature.
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3935 THREE-PHASE POWER MOSFET CONTROLLER
Functional Description
Motor Lead Protection. A fault detection circuit monitors the voltage across the drain to source of the external MOSFETs. A fault is asserted "low" on the output terminal, FAULT, if the drain-to-source voltage of any MOSFET that is instructed to turn on is greater than the voltage applied to the VDSTH input terminal. When a high-side switch is turned on, the voltage from VDRAIN to the appropriate motor phase output, VSX, is examined. If the motor lead is shorted to ground before the high side is turned on, the measured voltage will exceed the threshold and the FAULT terminal will go "low". Similarly, when a low-side MOSFET is turned on, the differential voltage between the motor phase (drain) and the LSS terminal (source) is monitored. VDSTH is set by a resistor divider to VDD. The VDRAIN is intended to be a Kelvin connection for the highside, drain-source monitor circuit. Voltage drops across the power bus are eliminated by connecting an isolated PCB trace from the VDRAIN terminal to the drain of the MOSFET bridge. This allows improved accuracy in setting the VDSTH threshold voltage. The low-side, drain-source monitor uses the LSS terminal, rather than VDRAIN, in comparing against VDSTH. The A3935 merely reports these motor faults. Fault Outputs. Transient faults on any of the fault outputs are to be expected during switching and will not disable the gate drive outputs. External circuitry or controller logic must determine if the faults represent a hazardous condition. FAULT. This terminal will go active "low" when any of the following conditions occur: VBAT overvoltage, VBAT undervoltage, VREG undervoltage, Motor lead short-to-ground, Motor lead short-to-supply (or battery), Bridge (or VDRAIN) open, VDD undervoltage, or Thermal shutdown. OVFLT. Asserts "high" when a VBAT overvoltage fault occurs and resets "low" after a recovery hysteresis. It has a highimpedance state when a thermal shutdown or VDD undervoltage occurs. The voltage at the OVSET terminal, VOVSET, controls the VBAT overvoltage set point VBAT(ov), i.e., VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov)(0), where KBAT(ov) is the gain (12) and VBAT(ov)(0) is the value of VBAT(ov) when VSET(ov) is zero (~22.4). For valid formula, all variables must be in range and below maximum operating specification. UVFLT. Asserts "high" when a VBAT undervoltage fault occurs and resets "low" after a recovery hysteresis. It has a highimpedance state when a thermal shutdown or VDD undervoltage occurs. OVFLT and UVFLT are mutually exclusive by definition. Current Sensing. A current-sense amplifier is provided to allow system monitoring of the load current. The differential amplifier inputs are intended to be Kelvin connected across a low-value sense resistor or current shunt. The output voltage is represented by: VCSOUT = ( ILOAD x AV x RS) + VOS where VOS is the output voltage calibrated at zero load current and AV is the differential amplifier gain of about 19.2. If either the CSP or CSN pin is open, the CSOUT pin will go to its maximum positive level. Shutdown. If a fault occurs because of excessive junction temperature or undervoltage on VDD or VBAT, all gate driver outputs are driven "low" until the fault condition is removed. In addition, the boost supply switch and the VREG are turned "off" until those undervoltages and junction temperatures recover. Boost Supply. VBOOST is controlled by an inner currentcontrol loop, and by an outer voltage-feedback loop. The current-control loop turns "off" the boost switch for 5 s whenever the voltage across the boost current-sense resistor exceeds 500 mV. A diode reverse-recovery current flows through the sense resistor whenever the boost switch turns "on", which could turn it "off" again if not for the "blanking time" circuit. Adjustment of this external sense resistor determines the maximum current in the inductor. Whenever VBOOST exceeds the predefined threshold, nominally 16 V, the boost switch is inhibited.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3935 THREE-PHASE POWER MOSFET CONTROLLER
Functional Description (cont'd)
Input Logic ENABLE xLO 0 1 1 1 1 X 0 0 1 1 xHI X 0 1 0 1 GLx 0 0 0 1 0 GHx 0 0 1 0 0 Mode of Operation All gate drive outputs low Both gate drive outputs low High side on Low side on XOR circuitry prevents shoot-through
Fault Responses Fault Mode No Fault Short-to-Battery Short-to-Ground Bridge (VDRAIN) Fault VREG Undervoltage VBAT Overvoltage VBAT Undervoltage' VDD Undervoltage' Thermal Shutdown' ENABLE Input X 1# 1$ 1% X X X X X FAULT 1 0 0 0 0 0 0 0 0 OVFLT 0 0 0 0 0 1 0 Z Z UVFLT 0 0 0 0 0 0 1 Z Z Boost Reg. ON ON ON ON ON OFF& OFF OFF OFF VREG Reg. ON ON ON ON ON ON OFF OFF OFF GHx " " " " " " 0 0 0 GLx " " " " " " 0 0 0
NOTES: x = "Little x "indicates A, B, or C phase. X = "Capital X " indicates a "don't care". Z = High-impedance state. " = Depends on xLO input, xHI input, and ENABLE. See Input Logic table. # = Short-to-battery can only be detected when the corresponding GLx = 1. This fault is not detected when ENABLE = 0. $ = Short-to-ground can only be detected when the corresponding GHx = 1. This fault is not detected when ENABLE = 0. % = Bridge fault appears as a short-to-ground fault on all motor phases. This fault is not detected when ENABLE = 0. & = Off, only because VBOOST VBAT is above the voltage threshold of the regulator's voltage control loop. ' = These faults are not only reported but action is taken by the internal logic to protect the A3935 and the system.
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3935 THREE-PHASE POWER MOSFET CONTROLLER
Package ED, 44-Pin PLCC
VREG
Package JP, 48-Pin LQFP
27 GHC 31 GHB 33 GLA 29 GLB 36 NC 35 NC 28 CC 25 NC 24 NC 23 NC 22 GLC 21 LSS 20 VDSTH 19 CSP 18 CSN 17 VDD 16 CSOUT 15 OVSET 14 NC 13 NC ENABLE 12 26 SC CHI 11 34 SA 32 CB 30 SB
GND
GND
GHA
42 GHB
44 GLA
40 GLB
CA
43 CB
SA
41 SB
6
4
3
5
2
1
NC 37
VDRAIN VBOOST BOOSTS
7 8 9
39 CC 38 GHC 37 SC 36 GLC 35 GND 34 GND 33 LSS 32 VDSTH 31 CSP 30 CSN 29 VDD
CLO 21 GND 22 GND 23 CHI 24 ENABLE 25 OVSET 26 CSOUT 28 AHI 18 BHI 19 BLO 20 NC 27
GHA 38 CA 39 VREG 40 VDRAIN 41 VBOOST 42 BOOSTS 43 BOOSTD 44 GND 45 VBAT 46 NC 47 NC 48
BOOSTD 10 GND 11 GND 12 VBAT 13 UVFLT 14 OVFLT 15 FAULT 16 ALO 17
OVFLT
UVFLT
Package LQ, 36-Pin SOIC
CSP VDSTH LSS GLC SC GHC CC GLB SB 1 2 3 4 5 6 7 8 9 36 CSN 35 VDD 34 CSOUT1 33 OVSET 32 ENABLE 31 CHI 30 CLO 29 BLO 28 BHI 27 AHI 26 ALO 25 FAULT 24 OVFLT 23 UVFLT 22 VBAT 21 GND 20 BOOSTD 19 BOOSTS
GHB 10 CB 11
GLA 12 SA 13 GHA 14 CA 15 VREG 16 VDRAIN 17 VBOOST 18
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
FAULT
CLO 10
5
6
7
8 BHI
1
2
3
4
ALO
AHI
BLO
NC
NC
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3935 THREE-PHASE POWER MOSFET CONTROLLER
A3935KED (PLCC)
Dimensions in Inches (for reference only)
Dimensions in Millimeters (controlling dimensions)
NOTES: 1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Terminals 1, 2, 11, 12, 22, 23, 34, and 35 are internally one piece. Supplied in standard sticks/tubes of 27 devices or add "TR" to part number for tape and reel.
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3935 THREE-PHASE POWER MOSFET CONTROLLER
A3935KJP (LQFP)
7 0 .20 .09 0.008 0.004
9 0.354 BSC 7 0.276 BSC
A
5 0.197 BSC
48
1 0.039 REF
1
2
.75 .45
0.030 0.018
.25 0.010 BSC Seating Plane Gauge Plane
.27 .17
0.011 0.007
.50 .020 BSC .15 .05
1.60 1.40 0.006 0.002
0.063 0.055
Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface)
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3935 THREE-PHASE POWER MOSFET CONTROLLER
A3935KLQ (SOIC)
Dimensions in Inches (for reference only)
Dimensions in Millimeters (controlling dimensions)
NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor's option within limits shown. 3. Supplied in standard sticks/tubes of 31 devices or add "TR" to part number for tape and reel.
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3935 THREE-PHASE POWER MOSFET CONTROLLER
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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